The Microarchitecture of FPGABased Soft ProcessorsFPGA基于软核处理器的微体系结构.pptVIP

下载本文档

1
0
约6.67千字
约 30页
2017-03-09 发布于上海
举报
版权申诉

The Microarchitecture of FPGABased Soft ProcessorsFPGA基于软核处理器的微体系结构.ppt

1、本文档共30页，可阅读全部内容。
2、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。
3、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
5、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
6、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
7、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
8、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

The Microarchitecture of FPGABased Soft ProcessorsFPGA基于软核处理器的微体系结构

The Microarchitectureof FPGA-Based Soft Processors Peter Yiannacouras Jonathan Rose Greg Steffan University of Toronto Electrical and Computer Engineering Processors and FPGAs Processors present in many digital systems Motivation for understanding soft processor architecture Soft processors are popular 16% of FPGA designs use a soft processor FPGA Journal, November 2003 This number has and will continue to increase Soft processors are end-user customizable Application-specific architectural tradeoffs Can be tuned by designers Don’t we already understand processor architecture? Not accurately/completely Accurate cycle-to-cycle behaviour Estimated area/power No clock frequency impact Not in FPGA domain Lookup tables vs transistors Dedicated RAMs and Multipliers fast Research Goals Generate soft processor implementations System for generating RTL Develop measurement methodology Metrics for comparing soft processors Develop understanding of architectural tradeoffs Analyze area/performance/power space Soft Processor Rapid Exploration Environment (SPREE) Input: Instruction Set Architecture (ISA) Description Input: Datapath Description Step 1.ISA vs Datapath Verification Step 2.Datapath Instantiation Step 3.Control Generation Output: Verilog RTL Description Back-end Infrastructure Metrics for Measurement Area: Equivalent Stratix Logic Elements (LEs) Relative silicon areas used for RAMs/Multipliers Performance: Wall clock time Cycle count ÷ clock frequency Arithmetic mean across benchmark set Energy: Dynamic Energy (eg. nJ/instr) Excluding I/O Trace-Based Verification Ensure SPREE generates functional processors Architectural Exploration Results Architectural Features Explored Hardware vs software multiplication Shifter implementation Pipelining Depth Organization Forwarding Validation of SPREE Through Comparison to Altera’s Nios II SPREE vs Nios II Architectural Features Explored Hardware vs software multiplication Shifter implementation Pipelining Depth Organiza