加法器53732.docVIP

加法器实验报告 源文件程序 library ieee; use ieee.std_logic_1164.all; entity addr4 is port(a:in std_logic_vector(4 downto 1); b:in std_logic_vector(4 downto 1); ci:in std_logic; sum:out std_logic_vector(4 downto 1); co:out std_logic); end addr4; architecture behavioral of addr4 is begin p1:process(a,b,ci) variable vsum:std_logic_vector(4 downto 1); variable carry:std_logic; begin carry:=ci; for i in 1 to 4 loop vsum(i):=(a(i)xor b(i))xor carry; carry:=(a(i)and b(i))or (carry and (a(i)or b(i))); end loop; sum=vsum; co=carry; end process p1; end behavioral;