Design Verification with SignalTapII(stp_final_4_1).pptVIP

Design Verification with SignalTap II FAE Training MaterialQuartus II Version 4.1 Agenda The “Logic Analyzer” in Your FPGA Soft IP is Added to Your Design to Emulate an External Logic Analyzer Using SignalTap II Agenda SignalTap II HDL Instantiation Instantiate SignalTap II Instance Directly in Your HDL In Quartus II v4.0 SignalTap II was Automatically Integrated with Your Design Use the MegaWizard to Create Custom Configuration SignalTap II HDL Flow Build MegaWizard Output SignalTap II HDL Flow (cont’d) 2. Instantiate and Connect MegaWizard Output in HDL The Signals Must Be Visible in the Module You Are Tapping SignalTap II HDL Flow (cont’d) 3. Compile Design In Quartus II Examine the SignalTap II Section of the Compilation Report 4. Automatically Generate an STP file Based on the MegaWizard Output Select Create SignalTap II File From Design Instance (File? Create Menu) To Allow You To Store Captured Data HDL Advantages/Disadvantages Design File Management is Made Easier – No STP File to Add to Projects You Have to Instantiate STP at the Hierarchical Boundary Where the Signals that you want to Tap are Counter Construct: Introduction Customer Problem: How Do I Trigger on an Event that Occurs ‘X’ Number of Times? In Quartus II v4.0: Use Multiple Trigger Levels With the Same Expression Repeated for Each Trigger Level Limited to 10 Trigger Levels Tedious In Quartus II v4.1: Build a Trigger Expression That Uses the Counter Construct in the Advanced Trigger Condition Editor Counter Construct : Example You Can Build a Trigger Condition That Triggers After an Event Occurs a User Defined Number of Times Triggers When BUS0 BUS1 are Equivalent 3 Times Counter Construct : Operation Mode Continuous Mode - The Input to the Event Counter Must be High for the Specified Number of Consecutive Clock Cycles Event Count Mode – The Input to the Event Counter Does not Have to be High for Successive Clock Cycles State Mode - The Internal Counter Increments When