DRAM Fundamental Application Overview DDR2.ppt

January 2008 QSH AE DRAM FundamentalApplication Overview Agenda SDRAM Fundamentals SDRAM Device Overview DRAM Cell - Physical View Cell Technology (Trench / Stack) DRAM Capacitor Types Memory-Architecture: Array Cell Array SDRAM Operation – SDRAM READ Timing SDRAM CAS Latency SDRAM Latencies What is DDR? SDRAM vs. DDR SDRAM Differential clocks / DQS DRAM Speed Sorts and Latencies: DDR DRAM Core Timings - Overview tRAS: Active to Precharge command tRP: Precharge command period tRC: Active to Active/Auto-Refresh command period tRRD: Active bank A to Active bank B command tRCD: Active to Read or Write (with and without Auto-Precharge) delay tCCD: CAS A to CAS B Command Period tWR: Write recovery time CL: CAS Latency tDQSS: Write command to 1st DQS latching transition RL: Read Latency (DDR-2); RL = AL + CL WL: Write Latency (DDR-2); WL = RL – 1tCK Additional core timings need to be observed. Refer to Spec or Model ! Additional features in DDR2 Reduced Power Supply Voltage Additional features in DDR2 4-bit Prefetch Architecture Additional features in DDR2 Differential Data Strobes Differential Data Strobes Read-Data-Strobe (RDQS) Additional features in DDR2 DDR like Operation without posted CAS- How to maximize Data/Command Bus Utilization? Write Latency Additional features in DDR2 Off-chip driver calibration (OCD) Off-chip driver calibration (OCD) Purpose: adjust off-chip driver strengths to optimum value for actual system environment (can be done once at initialization or repeated periodically to adjust for temperature shifts) Balance n- and p-channel driver strength Reduces timing errors from signal asymmetry Insure signal rise and fall time are similar Controller adjusts its own outputs before adjusting the DRAM Controller measures the driven voltage on the bus and programs the DRAM to the system optimum Controller must treat each DRAM separately therefore DRAM width must be known Simple inc/dec commands used to increase/decrease drive strength, issued by 4 bi