ASIC_Design_Flow.pptVIP

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  • 2017-04-04 发布于江苏
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ASIC_Design_Flow

ASIC DESIGN FLOW Liu Bo Senior Manager LTE modem Application Processor Multiband RF receiver 3-axis ?linear accelerometer Touch screen Controller ASICs ,the heart of Innovation! An?application-specific integrated circuit, or?ASIC is an?integrated circuit (IC) customized for a particular use. What’s ASIC Process evolution to VDSM 2003 90nm 2005 65nm 2007 45nm 2011 22nm 2009 32nm 100 400 1300 Process Design Complexity(Million Transistors) Moore’s Law In 1965, Gordon Moore, the cofounder of Intel, predicted that :the number of transistors on a chip will double approximately every 18 months. Moore’s law has inspired innovation for more than half a century and continues … From Sand to Chip ASIC DESIGN Pattern IDEA GDSII ASIC design house/service IC Fab ASIC Design FLow Design specification Design entry: Verilog Coding Simulation/ functional verification Chip integration/verification Synthesis/Pre layout timing/formal verification Scan Chain Insertion/ Test generation /Fault simulation Physical Design TO Sign-off Production-ready masks Design Verification DFT Physical Design ALU module ALU (a, b,c); Input a,b; Output c; DUT Stimulus Response Frontend Backend IDEA To Build an ASIC Team Design Verification DFT Physical Design Design Design specification Design entry: Verilog Coding Simulation/ functional verification Chip integration/verification Synthesis/Pre layout timing/formal verification Scan Chain Insertion/ Test generation /Fault simulation Physical Design TO Sign-off Production-ready masks What is verification? Verification is the process of verifying the transformation steps in the design flow are executed correctly. Verification Flow Design specification Design entry: Verilog Coding Simulation/ functional verification Chip integration/verification Synthesis/Pre layout timing/formal verification Scan Chain Insertion/ Test generation /Fault simulation Physical Design TO Sign-off Production-ready masks Verification Methodology The following coverage table

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