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Branch Anticipation using Loop Pipelining for Resource Constrained Systems.pdf

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Branch Anticipation using Loop Pipelining for Resource Constrained Systems

Branch Anticipation using Loop Pipelining forResource Constrained SystemsTed Zhihong YuNelson Luiz PassosEdwin Hsing-Mean ShaDept. of Computer Science EngineeringUniversity of Notre DameNotre Dame, IN 46556 AbstractLoop pipelining is an e ective technique to explore parallelism found in program loops,when designing high performance application speci c systems. However, branches withinloops may degrade the performance of pipelined architectures. It is an open question howapplications with multiple branches can be loop pipelined in the most ecient way. Thispaper presents properties, theories, and experiments of a new loop pipelining algorithm,called Branch Anticipation. This new method, based on the rotation technique, carriesout conditional resource sharing and reduces additional hardware requirements incurred bybranches within the loops. The optimization may require propagation of additional branchdecision signals along the schedule. We show that hardware constraints for such propagationmust be considered during the scheduling process. We further demonstrate that the methodis practical and achieves the same schedule length as the regular rotation scheduling with asmaller number of rotations and minimal additional hardware. 1 1 IntroductionComputation intensive applications usually depend on time-critical sections consisting of a loopof instructions. The schedule of the operations comprising the loop can be optimized in orderto improve its execution time, by exploring the parallelism embedded in repetitive patternsof the loop. This new schedule is then applied in the design of application speci c integratedcircuits (ASICs). However, the use of pipelined architectures may present a signi cant overheadif there are conditional statements in the loop. In this paper, we analyze the propagation of theoutcome of a condition evaluation along the schedule. A method, called branch anticipation,which reduces additional hardware requirements by using loop pipelining, is then p

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