ADI_DSP_tutorial2外文书.pdfVIP

Applications Engineering Notebook MT-201 One Technology Way ? P.O. Box 9106 ? Norwood, MA 02062-9106, U.S.A. ? Tel: 781.329.4700 ? Fax: 781.461.3113 ? Rev. 0 | Page 1 of 12 Interfacing FPGAs to an ADC Converter’s Digital Data Output by the Applications Engineering Group, Analog Devices, Inc. IN THIS NOTEBOOK Interfacing field programmable gate arrays (FPGAs) to analog-to-digital converter (ADC) output is a common engineering challenge. This notebook includes an overview of various interface protocols and standards as well as application tips and techniques for utilizing LVDS in high speed data converter implementations. The Applications Engineering Notebook Educational Series TABLE OF CONTENTS Interface Styles and Standards 2 General Recommendations 3 Typical Examples 4 Troubleshooting Tips 7 ADC with Missing Bit 14 7 ADC Frequency Domain Plot with Missing Bit 14 7 ADC Time Domain Plot with Missing Bit 14 8 ADC with Bit 9 and Bit 10 Shorted Together 8 ADC Frequency Domain Plot with Bit 9 and Bit 10 Shorted Together 9 ADC Time Domain Plot with Bit 9 and Bit 10 Shorted Together 9 Time Domain Plot with Invalid Data and Clock Timing 10 Zoomed-In Time Domain Plot with Invalid Data and Clock Timing 10 Using Adapter Boards 11 REVISION HISTORY 1/12—Revision 0: Initial Version POWER SUPPLY INPUT ANALOG INPUT DATA OUTPUT FPGA INTERFACE VREF GND CONTROL ADC CLOCK INPUT MT-201 Applications Engineering Notebook Rev. 0 | Page 2 of 12 INTERFACE STYLES AND STANDARDS Interfacing field programmable gate arrays (FPGAs) to analog- to-digital converter (ADC) digital data output is a common engineering challenge. The task is complicated by the fact that ADCs use a variety of digital data styles and standards. Single data rate (SDR) CMOS is very common for lower speed data interfaces, typically under 200 MHz. In this case, data is transitioned on one edge of the clock by the transmitter and received by the receive