delay-locked loop.pdf

ECE 658 Project - Delay Locked Loop Design Y. Sinan Hanay December 20, 2007 Chapter 1 Introduction Generation and distribution of clock signals inside the VLSI systems is one of the most important problems in the design of VLSI systems. Because of the process variations and interconnect parasitics, clock signals delays vary for dierent paths. The clock signals should have zero clock skew, that is to say all the clock signals should arrive at the inputs of registers at the same time. Otherwise latches and ip-ops get clock signal at dierent time instances. In order to circuit to operate correctly these dierences should be eliminated, ideally to zero. However it is not possible practically and 10% of the clock cycle is expended in order to compensate for clock skew[1]. To handle this problem, several solutions are proposed. One of which is usage of H-tree clock networks, in which conguration the distance to all circuit blocks is same thus the clock delay would be same. But this technique is hard to implement since the dierent fan- out requirements for dierent blocks and routing constraints. Also some CAD techniques and heuristics are used in the routing of the clock trees [6]. The reduction of clock skew is one of the important problems in the VLSI design. Passive techniques such as clock network optimization techniques cannot completely reduce the clock skew [2]. Phase-locked loops and delay-locked loops (DLL) are extensively used in VLSI circuits in order to decrease clock screw in the clock networks. DLL is a rst order loop that compares it`s input with a reference signal, than delay it `s output so that it can synchronize with the reference signal in a feedback fashion. DLL consists of 4 units: 1. Phase Detector 2. Charge Pump 3. Filter 4. Voltage Controlled Delay Line (VCDL) 1 It`s working principle is as follows: First, phase detect block compares the reference clock signal with the output signal, depending on the dierence , if reference signal is leadi