Novel Design and Verification of a 16 x 16-b Self- Repairable Reconfigurable Inner Product.pdfVIP

下载本文档

6
0
约2.68万字
约 6页
2017-04-11 发布于江苏
举报
版权申诉

Novel Design and Verification of a 16 x 16-b Self- Repairable Reconfigurable Inner Product.pdf

1、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。。
2、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
4、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
5、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
6、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
7、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

Novel Design and Verification of a 16 x 16-b Self- Repairable Reconfigurable Inner Product

Novel Design and Verification of a 16 x 16-b Self- Repairable Reconfigurable Inner Product Processor Rong Lin Martin Margala Department of Computer Science Electrical and Computer Engineering SUNY–Geneseo University of Rochester Geneseo, NY 14454 Rochester, NY 14627 lin@cs.geneseo.edu margala@ece.rochester.edu ABSTRACT A novel self-repairable and reconfigurable inner-product processor with low-power, fast CMOS circuits and DFT techniques is presented. It takes the advantage of recently proposed decomposition based arithmetic circuit design approach for simple implementation of the reconfigurations, component replacements, and high-quality tests. The processor can be dynamically reconfigured for two types operations: 4 x 8 x 8-b inner product computation and 16 x 16-b multiplication. The self-repair is provided by choosing a fault- free one from 17 possible architectures during the test, which covers more than 52% transistors for the specified faults. Only one extra bit is needed for all reconfigurations, repairs, and tests. The proposed exhaustive DFT technique greatly reduces the test vector length, from 17*2 32 to 1.5*2 13 , which is as short as that required by the pseudo-exhaustive DFT method recently reported in literature. Keywords Reconfigurable, Decomposition Algorithms, Self-Repair, VLSI, Arithmetic Circuits, Image Processing, Fault Tolerance 1. INTRODUCTION Fast, low-power, low-cost, high-yield processors for multiplication and inner-product computation have become increasingly important to the rapidly growing computing industry, particularly for SoC designs [1, 2, 11-14] . The main hurdles preventing an efficient design of such processors include irregularity of the architectures, large VLSI area, high complexity of testing, and difficulty of fault recovering. In this paper we present the design and tests of a highly regular, 16 x 16-b repairable and reconfigurable inner product processor/multiplier architecture and design using low-power, fast C