FPGA程序.docVIP

top_clock.v module top_clock(clk,,SEG,DIG,key); input clk; input[3:0] key; output [7:0] SEG,DIG; wire clk_s; wire key_out; key key_inst ( .clk(clk) , // input clk_sig .keyin(key) , // input [3:0] keyin_sig .keyout(key_out) // output [3:0] keyout_sig ); s s_inst ( .clk(clk) , // input clk_sig .s(clk_s) // output s_sig ); clock clock_inst ( .Clk0(clk) , // input Clk0_sig .Clk1(clk_s) , // input Clk1_sig .SEG(SEG) , // output [7:0] SEG_sig .DIG(DIG) , // output [7:0] DIG_sig .key(key_out) // input [3:0] key_sig ); Endmodule Key.v module key (clk,keyin,keyout); input clk; input [3:0] keyin; output reg [3:0] keyout; reg [19:0] cnt; reg [3:0] key_tem1; reg [3:0] key_tem2; always @ (posedge clk) begin cnt = cnt + 1; key_tem2 = key_tem1; keyout = (key_tem1 (!key_tem2)); if (cnt ==20hfffff) key_tem1 = keyin; end endmodule s.v module s (clk,s); input clk; output reg s; reg [27:0] cnt; always @ (posedge clk) begin if(cnt = 28h17D7840) begin s = ~s; cnt = 0; end else cnt = cnt + 1; end endmodule clock.v module clock(Clk0,Clk1,SEG,DIG,key); input Clk0,Clk1; input[3:0] key; output [7:0] SEG,DIG; //DIG?? SEG?? reg [23:0] q; //?????? reg [23:0] temp; //???????? reg [2:0] SCAN_R; reg [3:0] SEG_M [5:0]; reg [7:0] SEG_DR; reg [12:0] CNT_R0; reg [12:0] CNT_R1; reg [23:0] Clk2; reg [7:0] SEG,DIG; always@ ( posedge Clk0 ) //???? begin temp=q; if(key[0]==1)//?? temp=0; else if(key[1]==1)//??? temp[23:16]=temp[23:16]+1b1; else if(key[2]==1)//??? if(temp[11:8]==4h9) begin temp[11:8]=0; temp[15:12]=temp[15:12]+1b1; end else begin temp[15:8]=temp[15:8]+1b1;