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High-Speed and Low-Power Split-Radix FFT
864 IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 51, NO. 3, MARCH 2003
High-Speed and Low-Power Split-Radix FFT
Wen-Chang Yeh and Chein-Wei Jen
Abstract—This paper presents a novel split-radix fast Fourier
transform (SRFFT) pipeline architecture design. A mapping
methodology has been developed to obtain regular and modular
pipeline for split-radix algorithm. The pipeline is repartitioned to
balance the latency between complex multiplication and butterfly
operation by using carry-save addition. The number of complex
multiplier is minimized via a bit-inverse and bit-reverse data
scheduling scheme. One can also apply the design methodology
described here to obtain regular and modular pipeline for the
other Cooley–Tukey-based algorithms.
For an (= 2 )-point FFT, the requirements are log
4
1
multipliers, 4 log
4
complex adders, and memory of size 1
complex words for data reordering. The initial latency is + 2
log
2
clock cycles. On the average, it completes an -point FFT
in clock cycles. From post-layout simulations, the maximum
clock rate is 150 MHz (75 MHz) at 3.3 v (2.7 v), 25 C (100 C) using
a 0.35- m cell library from Avant!. A 64-point SRFFT pipeline de-
sign has been implemented and consumes 507 mW at 100 MHz, 3.3
v, and 25 C. Compared with a radix-2
2
FFT implementation, the
power consumption is reduced by an amount of 15%, whereas the
speed is improved by 14.5%.
Index Terms—Low power FFT, split-radix FFT.
I. INTRODUCTION
T
HE FAST Fourier transform (FFT) and its inverse (IFFT)
are essential in the field of digital signal processing.
Recently, due to the popularity of the orthogonal frequency
division multiplex (OFDM) system, the demand for high-speed
and low-power FFT emerges from various applications.
According to the European digital video/audio broadcasting
(DVB-T/DAB) standards, an OFDM system may require FFT
length ranging from 256- to 8192-point. Wireless local area net-
work (WLAN) and HIPERLAN/2 systems require high-speed
and low-power FFT/IFFT design [1
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