EDA技术P5_VHDL行为与结构描述.pptVIP

EDA技术;VHDL 的行为描述与结构描述;;;;;;;;;;;;;;;;VHDL语言的并行执行;;;;;;;;;;;;ENTITY fulladd IS PORT ( x, y, cin: IN STD_LOGIC; sum, cout: OUT STD_LOGIC); END ENTITY fulladd;;;;;;;;;课堂练习;课堂练习-参考答案;ARCHITECTURE structural OF adder IS COMPONENT adder IS PORT ( x, y : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Cin : IN STD_LOGIC; Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Cout : OUT STD_LOGIC ); END COMPONENT; SIGNAL carry: STD_LOGIC; BEGIN c0: adder PORT MAP ( x =x ( 3 downto 0), y = y (3 downto 0), cin = Cin, sum=Sum(3 downto 0), Cout = carry