基于veriloghdl的异步FIFO论文.docVIP

PAGE   PAGE \* MERGEFORMAT 4 (此文档为word格式，下载后您可任意编辑修改！) 题 目 基于verilog and accomplish asynchronous FIFO based on Verilog HDL Abstract In modern IC design, particularly in the communications module and peripheral chip design, multiple clock domains of the inevitable. When data passes from one clock domain to another domain, and the target clock domains are not associated with the source clock domain, these domains are not related movements, thus eliminating the possibility of simultaneous operation and allows the system to enter the sub-repeat steady-state, causing disorder on the