Verilogexamples.PDF

Verilog examples //*************************************************// // 来自：《Verilog，HDL程序设计教程》by王金明 // 备注：以下程序尚未进行验证 //*************************************************////4位全加器 module adder4(sum, cout, ina, inb, cin); output[3:0] sum; output cout; input[3:0] ina, inb; input cin; assign {cout, sum} = ina + inb + cin; endmodule//4位计数器 module counter4(out, reset, clk); output[3:0] out; input reset, clk; reg[3:0] out; always @(posedge clk) begin if(reset) out = 0; else out = out + 1; end endmodule//4位全加器的仿真程序 `timescale 1ns/1ns `include adder4.v module adder4_testbench; reg[3:0] a, b; reg cin; wire[3:0] sum; wire cout; integer i, j;adder4 adder(sum, cout, a, b, cin); always #5 cin = ~cin;initial begin a = 0; b = 0; cin = 0; for(i = 1; i 16; i = i + 1) #10 a = i; endinitial begin for(j = 1; j 16; j = j + 1) #10 b = j; endinitial begin $monitor($time,,,%d + %d + %b = {%b, %d}, a, b, cin, cout, sum); #160 $finish; end endmodule//4位计数器的仿真程序 `timescale 1ns/1ns `include counter4.v module counter4_testbench; reg clk, reset; wire[3:0] out; parameter DELAY = 100;counter4 mycount(out, reset, clk);always #(DELAY/2) clk = ~clk;initial begin clk = 0; reset = 0; #DELAY reset = 1; #DELAY reset = 0; #(DELAY*20) $finish endinitial $monitor($time,,,clk=%d reset=%d out=%d, clk, reset, out); endmodule//“与-或-非”门电路 module AOI(F, A, B, C, D); output F; input A, B, C, D; wire A, B, C, D, F; assign F = ~((AB)|(CD)); endmodule//用case语句描述的4选1数据选择器 module mux4_1(out, in0, in1, in2, in3, sel); output out; input in0, in1, in2, in3; input[1:0]; reg out; always @(in0 or in1 or in2 or in3 or sel) case(sel) 2b00: out = in0; 2b01: out = in1; 2b10: out = in2; 2b11: out = in3; default: out = 2bx; endcase endmodule//同步置数、同步清零的计数器 module count(out, data, load, reset, clk); output[7:0] out; input[7:0] data; input load, reset, clk; reg[7:0] out; always @(posedge clk) begin if(reset) out = 8h00; else if(load) out = data; e