超大规模集成电路中低功耗设计与分析.docVIP

超大规模集成电路中低功耗设计与分析 摘要 摘 要 随着IC设计的规模更大，速度更快，以及便携式设备的广泛需求，设计中功耗的问题越来越凸现出来，所以在整个设计流程中就需要对功耗进行分析和低功耗设计，这些技术可以保证芯片的每一部分都能高效、可靠、正确地工作。 选择合适的低功耗手段，必须以细致的功耗预估为前提，并且也要掌握工具的适用范围和能达到的低功耗底限。在流程中尽可能早的分析出功耗需求，可以避免和功耗相关的设计失败。通过早期的分析，可以使用高层次的技巧来降低大量的功耗，更容易达到功耗的要求。 本论文围绕数字CMOS电路的功耗问题进行展开，主要分成两大部分。 首先针对超大规模集成电路中的功耗分析进行探讨，介绍了在RTL级、门级不同层次上对功耗进行分析的方法和对实际设计的指导意义，并对一个450万门的超大规模芯片在各层次上进行功耗分析，并和流片后测试得到的结果有着很好的吻合。 然后是对低功耗进行了一些结构上的设计。动态电压缩放（DVS）技术是一种通过将不同电路模块的工作电压调低到恰好满足系统最低要求来实时降低系统中不同电路模块功耗的方法，有着良好的应用前景。本论文实现了一款动态电压缩放（DVS）电路，可应用于突发吞吐量工作模式的处理器，通过和一个电路实例的整体仿真，验证了该DVS电路的低功耗效果。 关键字：低功耗；功耗分析；动态电压缩放 I Abstract Abstract Liu Hainan (Microelectronics and Solid-State Electronics) Directed by Professor Zhou Yumei As the design of IC go into larger and faster, the issue about power consumption is more critical. It is necessary to analysis the power accurately and manage low power techniques in every step of the design flow, so as to assure the efficient, reliable and correct function. Choosing the appropriate low power solutions depends on careful power analysis as well as understanding the capabilities of available tools. Analyzing power requirements as early as possible in the design flow helps avoid power related disasters. Early analysis also makes power goals easier to attain because higher-level techniques save the greatest amount of power. The thesis is made up of two main parts based on the discussion of the digital CMOS power consumption. First of all, this thesis introduces and demonstrates a top-down VLSI design methodology for power analysis, discuss the method to estimate the power on RTL and gate level, which could serve as a guide to the floorplan and place amp; route. And estimate the power consumption about a 4.5 million VLSI on several level, draw some conclusion from comparing the test result of the fabricated chip. In the second, completed a low power technique on the structure level. Dynamic Voltage Scaling is a te