基于EDA的数字电子钟设计.doc

石河子大学 王刘龙  PAGE \* MERGEFORMAT 1 摘 要 数字时钟，就是以数字显示取代模拟表盘的钟表，在显示上它用数字反应此时的时间,它还能同时显示时，分，秒,且能够对时，分，秒准确进行校时。 数字时钟是一种用数字电路技术实现时、分、秒计时的装置。与机械式时钟相比具有更高的准确性和直观性，且无机械装置，具有更长的使用寿命，已得到广泛的使用。数字钟从原理上讲是一种典型的数字电路，一般是由振荡器、分频器、计数器、显示器等几部分组成。其中包括了组合逻辑电路和时序电路。数字钟的设计方法有许多种，例如：可用中小规模集成电路组成电子钟；也可以利用专用的电子钟芯片配以显示电路及其所需要的外围电路组成电子钟；还可以利用单片机来实现电子钟等等。 本设计采用EDA技术，以硬件描述语言Verilog HDL为系统逻辑描述手段设计文件，在QUARTUS II工具软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA的数字钟。 数字时钟以其体积小、重量轻、抗干扰能力强、对环境要求高、高精确性、容易开发等特性，在工业控制系统、智能化器仪表、办公自动化等诸多领域取得了极为广泛的应用，诸如定时自动报警、按时自动打铃、时间程序自动控制、定时广播、自动启闭路灯、定时开关烘箱、通断动力设备、甚至各种定时电气的自动启用等。 关键词：EDA、QuartusII、Verilog HDL、FPGA芯片、数字时钟等  PAGE \* MERGEFORMAT 36 Abstract Digital clock is with digital display to replace analog dial watch, in the show it with digital reaction at this time, it can display at the same time, minutes and seconds, and can pair, minutes and seconds precise timing. Digital clock is a digital circuit technology to achieve time, minutes and seconds of the device. Compared with the mechanical clock has higher accuracy and intuitive, and no mechanical device, has a longer life, has been widely used. Digital clock from the principle of speaking is a typical digital circuit, generally by the oscillator, frequency divider, counter, display and other parts of the composition. The combination logic circuit and the sequential circuit are included in the circuit. Digital clock design, there are many methods. For example: available small scale integrated circuit composition electronic clock; can also use special chip electronic clock with to display circuit and its peripheral circuit composed of electronic clock; can also be used to achieve single-chip electronic clock and so on. This design using EDA technology, the Hardware Description Language Verilog HDL logic system description method of design documents, in the Quartus II software environment by top-down design method, by all the basic modules work together to build a based on FPGA digital clock. Digital clock with the v