数字逻辑（邓建）03-01-03.pptVIP

* 课后作业 3.11 可以只画逻辑电路图 3.12 可以只画逻辑电路图 3.13 3.15 或门的输入数为2 3.59 * * * * * * * * * * If A and B are 0, at least both nMOS transistors are OFF, breaking path from Y to GND. Both pMOS transistors ON, creating path from Y to VDD. So output Y is 1. * 4、CMOS与非门 A B (A B) A B F 2 parallel pMOS transistors between Y and VDD 2 series nMOS transistors between Y and VSS Parallel pMOS Series nMOS pB pA nA nB VDD VSS “Pull Up” pMOS gates used when output needs to be HIGH for LOW input(s) “Pull Down” nMOS gates used when output should be LOW for HIGH input(s) * 4、CMOS与非门 工作原理： 1、A、B至少有一个为低 T1、T3至少有一个截止，