Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering 外文参考文献.docVIP

VLSIDesign,2002Vol.15(2),pp.547–553 ReductionofPowerDissipationinDynamicBiCMOSLogic GatesbyTransistorReordering S.M.REZAULHASAN,a,*andYUFRIDINWAHAB,b aDepartmentofElectricalandComputerEngineering,CollegeofEngineering,UniversityofSharjah,UniversityCity,P.O.Box27272,Sharjah,United ArabEmirates; bSilterraInc.,KulimHighTechnologyPark,Kulim,Kedah,Malaysia (Received13April2001;Revised3May2002) This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capabilityand NP