计算机设计与实践——32位ALU设计精要.pptx

32位ALU设计;module alu(alu_da,alu_db,alu_clt,alu_shift,alu_zero_out,overflow_out,alu_dc ); input [31:0]alu_da; input [31:0]alu_db; input [3:0]alu_clt; input [4:0]alu_shift; output reg alu_zero_out; output reg overflow_out; output reg [31:0]alu_dc; wire alu_zero; wire overflow; wire [31:0]alu_and;//与结果 wire [31:0]alu_or;//或结果 wire [31:0]alu_xor;//异或结果 reg [31:0]alu_sll;//左移结果 reg [31:0]alu_srl;//右移结果 reg [31:0]alu_sra;//算数右移 wire [31:0]alu_add;//加减运算结果 wire c2;//加法器进位输出 reg Sub;//加法器控制端 wire [31:0]alu_db_n;//b取非运算 reg [31:0]alu_db_mux;//b的加减选择运算 wire ci;//进位输出 always@(*) begin case(alu_clt)