数电课件Lec09Chap4.pptVIP

Jin. UESTC Digital Logic Design and Application * Digital Logic Design and ApplicationLecture #09 Timing Hazards Chap. 4 Summary UESTC, Spring 2014 * 4.4 Timing Hazards Steady-state Behavior Transient Behavior Hazard(冒险) 数字电路中在某瞬间可能出现非预期信号的现象，也就是违背真值表规定的逻辑电平的情况，冒险也可以看成为一种过渡现象，一种干扰。 A A’ A F F glitch 当一个信号通过两条或两条以上路径去影响输出逻辑值，但由于各个路径延时不同而造成的作用时间之差称为竞争，输出信号出现的险象正是这两条路径竞争的结果。 * 4.5.1 Static Hazards Static 1-Hazards Static 0-Hazards In “AND-OR” circuits In some conditions, the output may be written as F = B+B’ In some conditions, the output may be written as F = B·B’ In “OR-AND” circuits A static hazards (静态冒险)is the possibility of an output producing a glitch when it is expected steady. 如果输入信号变化前后稳定状态输出的逻辑值相同，而在转换瞬间出现尖脉冲，称为静态冒险。 * 1 1 G2 = B G1 = B’ Static 1-Hazards * 4.5.2 Finding Static Hazards Using Maps Z XY 00 01 11 10 0 1 1 1 1 1 (X+X’) correspond to the sum of adjacent cells in K-Map, so the static hazard can be detected by studying the adjacent “circle”. And it can be eliminated by adding consensus term. F = X·Z’ + Y·Z + X·Y If X=1 and Y=1, then F=Z’+Z Static 1-Hazards +1 * AB CD 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 1 1 4.5.2 Finding Static Hazards Using Maps If cost is not a problem, a brute-force method of obtaining a hazard-free realization is to use the complete sum. Other ways to eliminate Static Hazards 电路稳定后加入取样脉冲，在取样脉冲作用期间输出的信号才有效，可以避免毛刺影响输出波形。 * Other ways to eliminate Static Hazards 输出端加小电容 在对输出波形边沿要求不高时，可在输出端加一个滤波电容，以滤除毛刺信号，但是将会使输出信号的边沿变坏。 * * Chapter 4 Summary 4.1 Switching Algebra Axioms Theorems Standard Representations of Logic Functions Product term, Sum of Products Sum term, Product of Sums Normal term, Minterm and Maxterm Canonical Sum (Product) Complement and Duality Complete is another discription for the same logic problem Duality is totally another function An example of God/Bad Man * Chapter 4 Brief Summary 4.2 Combinational-Circuit Analysis Logic diagram ? formal description of t