源同步接口约束.ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * If they want to see it derived: (1) input delay max = Board Delay – Board clock skew + Tco(max) (2) slack = required time - data arrival time If slack is set to zero, then: (3) data required time = data arrival time Thus, (4) latch edge – Ttotal_tsu = launch edge + input delay max And (5) Input delay max = latch edge – launch edge – Ttotal_tsu For hold (3) still applies: (3) Data required time = data arrival time Thus (6) Latch edge + Ttotal_th = launch edge + input delay min Since latch and launch are typically 0 (7) Input delay min = Ttotal_th * If they want to see it derived: (1) input delay max = Board Delay – Board clock skew + Tco(max) (2) slack = required time - data arrival time If slack is set to zero, then: (3) data required time = data arrival time Thus, (4) latch edge – Ttotal_tsu = launch edge + input delay max And (5) Input delay max = latch edge – launch edge – Ttotal_tsu For hold (3) still applies: (3) Data required time = data arrival time Thus (6) Latch edge + Ttotal_th = launch edge + input delay min Since latch and launch are typically 0 (7) Input delay min = Ttotal_th * * * * * * * * * * * Now we are going to check what SDC timing constraints we would apply to the following design situations. * * * * * * * * * * * * Instead of resetting the state machine back to your idle state, you send it to some other state, possibly an illegal one. * * Example, you have a path that is part of test logic. The only reason the path is used, is when you are in a test mode in which the clock frequency is actually lower than the design frequency. These paths you would want to fitter to exclude from analysis. * * * * * * Use early and late to indicate maximum and minimum PCB propagation delay times. * * * * * * * * These undefined clocks could be purposefully or accidentally created. For example, a “clock” could have been created due to incorrect HDL coding. * * * Now we are going