Module3 F28x–Digital IO.ppt

C281x Block Diagram TMS320F2812 Memory Map C28x GPIO Register Structure C28x GPIO Pin Assignment C28x GPIO Functional Block Diagram C28x GPIO MUX/DIR Registers C28x GPIO Data Registers C28x Oscillator / PLL Clock ModulePLLCR @ 7021h Peripheral Clock Control RegisterPCLKCR @ 701Ch High / Low – Speed Peripheral Clock Pre-scale RegistersHISPCP @ 701Ah / LOSPCP @ 701Bh Watchdog Timer Resets the C28x if the CPU crashes Watchdog counter runs independent of CPU If counter overflows, reset or interrupt is triggered CPU must write correct data key sequence to reset the counter before overflow Watchdog must be serviced (or disabled) within ~4,3ms after reset (30 MHz external clock) This translates into 6.3 million instructions! Watchdog Timer Module Watchdog Timer Control Register WDCR @ 7029h Resetting the Watchdog WDKEY @ 7025h Allowable write values: 55h - counter enabled for reset on next AAh write AAh - counter set to zero if reset enabled Writing any other value immediately triggers a CPU reset Watchdog should not be serviced solely in an ISR If main code crashes, but interrupt continues to execute, the watchdog will not catch the crash Could put the 55h WDKEY in the main code, and the AAh WDKEY in an ISR; this catches main code crashes and also ISR crashes WDKEY Write Results System Control and Status RegisterSCSR @ 7022h Low Power Modes Low Power Mode Control Register 0LPMCR0 @ 701Eh Low Power Mode Control Register 1LPMCR1 @ 701Fh Low Power Mode Exit Lab 2: Digital Output on Port B0...B7 Lab 2: Digital Output on Port B0...B7 Lab Exercise 2A Lab 3: Digital Input (GPIO B15..B8) Lab 3A Lab 3A (cont.) Lab 3B 3 - * 32-Bit-Digital Signal Controller TMS320F2812 Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH) Module 3: F28x –Digital I/O 32x32 bit Multiplier Sectored Flash A(18-0) D(15-0) Program Bus Data Bus RAM Boot ROM 22 32-bit Auxiliary Registers 3 32 bit Timers Realtime JTAG CPU Register B