THC63LVD104C应用说明.pdf

THAN0064_Rev.1.40_E Application Note THAN0064_Rev1.40_E THC63LVD103(D)/THC63LVD105/THC63LVD104S(C) ApplicationNote System Diagram and PCB Design Guide Line Copyright© 2009 THine Electronics, Inc. 1/11 THine Electronics, Inc. THAN0064_Rev.1.40_E Contents 1.TTL Data Timing Diagram P3 2.LVDS DATA Timing Diagram P4 3.Example of System Diagram 1)10 bit TTL/CMOS Level Input P5 2)10 bit Small Swing Level Input P6 3)8 bit TTL/CMOS Level Input P7 4.NOTE P8,9 5. PCB Design Guide Line for LVDS P10 Copyright© 2009 THine Electronics, Inc. 2/11 THine Electronics, Inc. THAN0064_Rev.1.40_E 1. TTL DATA Timing Diagram Following are THC63LVD103(D)/THC63LVD105 TTL data input timing example for SXGA+(1400 x 1050). HSYNC DE DotCLK R1x/G1x/B1x #1 #2 #3 #4 1398 #1399 #1400 #1 #2 #1399 #1400 TFT Panel (1400 x 1050) Note: Red Green Blue MSB R9 G9 B9 R8 G8 B8 R7 G7 B7 R6 G6 B6 R5 G5 B5