A case study for the verification of complex timed circuits IPCMOS ￡.pdfVIP

A case study for the verification of complex timed circuits: IPCMOS  Marco A. Pe˜nay and Jordi Cortadellaz and Enric Pastory and Alexander Smirnovz y Department of Computer Architecture z Department of Software Technical University of Catalonia Technical University of Catalonia 08860 Castelldefels (Barcelona), Spain 08034 Barcelona, Spain fmarcoa, enricg@ac.upc.es fjordic, alexs g@lsi.upc.es Abstract for absolute timing analysis [10]. The verification of a n -stage pulse-driven IPCMOS pipeline, for 2. Assume-guarantee paradigm to perform a hierarchical verifi- any n 0, is presented. The complexity of the system is 32n tran- cation of large systems by means of abstractions. sistors and delay information is provided at the level of transistor. The correctness of the circuit highly depends on the timed behav- 3. Mathematical induction to prove the correctness of infinite- ior of its components and the environment. To verify the system, state systems. three techniques have been combined: (1) relative-timing-based These techniques have been used to verify the IPCMOS control verification from absolute timing information [13], (2)