基于FPGA地字串行FIR滤波器地实现.PDF

第 27 卷 第 6 期 北 　方 　交 　通 　大 　学 　学 　报 Vol. 27 No. 6 　 　 　 　 　 　 　 　 　 　 　 　 2003 年 12 月 JOURNAL OF NORTHERN J IAO TON G UN IV ERSIT Y Dec. 2003 ( ) 文章编号 2003 基于 FPGA 的字串行 FIR 滤波器的实现 罗耀国 ,娄淑琴 (北京交通大学 电子信息工程学院 ,北京 100044) 摘 　要 :根据字串行算法 ,使用字串行加法器、字串行乘法器和延时器基本功能模块 ,构建了一 种基于 FPGA 的字串行 FIR 滤波器. 与传统的位串行方式相比 ,构建的字串行 FIR 滤波器提 高了运行速度 ,减少了硬件消耗 ,可更好的协调速度与占用面积的关系. 并通过几种 5 阶 FIR 滤波器实现性能的比较 ,得出字长 N = 2 的字串行 FIR 滤波器具有最小的面积 —时间积. 关键词 :信息处理技术 ;现场可编程门阵列 ;字串行 ;位串行 ; FIR 滤波器 中图分类号: TN431. 2 　　　文献标识码 :B The Implementation of Digit-Serial FIR Filters Based on FPGA L UO Yao- guo , L OU S hu- qi n ( School of Electronics and Information Engineering , Beijin g Jiao Tong University , Beijin g 100044 ,China) Abstract :The implementation of a digit- serial fir filter based on FA GA was proposed. According to digit- serial arithmetic , the digit- serial FIR filter was designed with the foundational function modules that included digit- serial adder , digit- serial multiplier and delay circuit . Compared with the traditional bit- serial method , the response speed of this digit- serial FIR filters has been im proved and the hardware consumption has been decreased. At the same time , the relationship be tween speed and area could be adjusted in a better manner. And throu gh the comparison of perfor mance for several 5-tap FIR filter , it can be concluded that the digit- serial FIR filters with N = 2 have the minimum area-time product . Key words :information proce