3.1 MOS器件.pptVIP

* 0.25 mm CMOS Capacitances W/L=0.36um/0.25um的NMOS（LD,S＝0.625u） 根据设计规则，计算出栅和漏端的电容 如果考虑反偏电压和适当的版图优化，二者基本相等，漏端电容甚至更小些 * Fourth terminal, body (bulk on previous slide) - substrate, not shown. Assumed connected to the appropriate supply rail, GND for NMOS, VDD for PMOS Electrons flow from source to drain – so current is referenced drain to source (IDS) Performs very well as a switch, little parasitic effects Today: STATIC (steady-state view) and later DYNAMIC (transient view) VGS 0.43 V for off VGS 0.43 V for on * Conductivity of the channel is modulated by the gate voltage - the larger