verilog5种不同的寄存器（国外英文资料）.doc

verilog5种不同的寄存器（国外英文资料） Verilog HDL register type representation The 2007-11-22 14:48 There are five different register types. * reg * integer * time * real * realtime Reg register type The register data type reg is the most common type of data. The reg type is illustrated using the reserved word reg as follows: [MSB] reg1, reg2. MSB and LSB define the scope, and both are often numeric expressions. The scope definition is optional; If no scope is defined, the default value is a register. Such as: [3:0] Sat; / / Sat is a four-bit register. Reg Cnt. / / 1 register. [1:32] Kisp, Pisp, Lisp; Registers can be arbitrarily long. The values in the register are usually interpreted as unsigned Numbers, for example: Reg [1:4] Comb; ... Comb = 2; / / Combs value is 14 (1110) and 1110 is a complement of 2. Comb = 5; The value of / / Comb is 15 (0101). 2. The memory Memory is a register array. Memory USES the following instructions: [MSB] memory1 [upper1: lower1], [upper2: lowercase 2]. Such as: [0:3] MyMem [0:06] / / MyMem is an array of 64 registers. Reg Bog, [1:5] / / Bog is an array of five registers. Both MyMem and Bog are memory. The dimension of the array cannot be greater than 2. Note that the memory belongs to the register array type. The line network data type has no corresponding memory type. A single register specification can be used to either specify the register type or to specify the type of storage. Parameter ADDR_SIZE = 16, WORD_SIZE = 8; Reg [1: WORD_SIZE] RamPar [ADDR_SIZE], DataReg; RamPar is a memory, 16 8-bit register arrays, and DataReg is an 8-bit register. Note the difference in the assignment statement: the memory assignment cannot be done in an assignment statement, but registers can. Therefore, you need to define an index when the memory is assigned. The next example illustrates the difference between them. Reg [1:5] Dig; / / Dig is a five register. ... Dig = 5 b11011; All of these assignments are correct, but the following assignment is incorrect: R