通用寄器组.docVIP

library ieee; use ieee.std_logic_1164.all; entity decoder_3_8 is port( I_L:in std_logic_vector(2 downto 0); S1,S2_L,S3_L:in std_logic; F_L:out std_logic_vector(7 downto 0)); end decoder_3_8; architecture decoder_3_8p of decoder_3_8 is signal F_s :std_logic_vector(7 downto 0); begin process(I_L,S1,S2_L,S3_L) begin case I_L is when 000 = F_s = when 001 = F_s = when 010 = F_s = when 011 = F_s = when 100 = F_s = when 101 = F_s = when 110 = F_s = when 111 = F_s = when others = F_s end case; if (S1 and not S2_L and not S3_L)=1 then F_L = F_s; else F_L = end if; end process; end decoder_3_8p; --底层16位寄存器 library ieee; use ieee.std_logic_1164.all; entity register16 is port( clk,clear,cs,wr:in std_logic; d: in std_logic_vector(15 downto 0); q: out std_logic_vector(15 downto 0)); end entity register16; architecture registerp of register16 is signal qin : std_logic_vector(15 downto 0); begin process(clk,clear,cs,wr,qin) begin if clear = 0 then qin = 0000000000000000; elsif rising_edge(clk) then if wr = 0 and cs = 0 then qin = d; end if; end if; if cs = 0 and wr = 1 then q = qin; else q= ZZZZZZZZZZZZZZZZ; end if; end process; end architecture registerp; library ieee; use ieee.std_logic_1164.all; entity registergroup is port( A:in std_logic_vector(15 downto 0); B:out std_logic_vector(15 downto 0); C:in std_logic_vector(2 downto 0); clk2,clear2,wr2,sta,stb,stc:in std_logic); end entity registergroup; architecture r_group of registergroup is signal t:std_logic_vector(7 downto 0); component decoder_3_8 port( I_L:in std_logic_vector(2 downto 0); S1,S2_L,S3_L:in std_logic; F_L:out std_logic_vector(7 downto 0)); end component; component register16 port( clk,clear,cs,wr:in std_logic; d:in std_logic_vector(15 downto 0); q:out std_logic_vector(15 downto 0)); end component; begin g1:decoder_3_8 p