VHDL数字秒表.docVIP

数字秒表 一 设计任务 library ieee; use ieee.std_logic_1164.all; entity CLKGEN is port(clki:in std_logic; clko:out std_logic); end CLKGEN; architecture behav of CLKGEN is signal q:integer range 0 to 9999; begin process(clki,q) begin if clkievent and clki = 1 then q=q+1; end if; if q = 1 then clko = 0; else clko = 1; end if; end process; end behav; 时钟分频电路模块仿真 时钟分频电路模块仿真结果 3.2六进制计数控制模块 程序 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT6 IS PORT( CLK,RST,EN : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT6; ARCHITECTURE behav OF CNT6 IS BEGIN PROCESS (CLK,RST,EN) VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RST = 1 THEN Q := (OTHERS=0); ELSIF CLKEVENT AND CLK = 1 THEN IF EN = 1 THEN IF Q5 THEN Q := Q + 1; ELSE Q := (OTHERS=0); END IF; ELSE Q := Q ; END IF; END IF; IF Q = 0101 THEN COUT = 0; ELSE COUT = 1; END IF; DOUT= Q ; END PROCESS; END behav; 六进制计数控制模块仿真 六进制计数控制模块仿真结果 3.3十进制计数控制模块 程序 ENTITY CNT10 IS PORT( CLK,RST,EN : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT10; ARCHITECTURE behav OF CNT10 IS BEGIN PROCESS (CLK,RST,EN) VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RST = 1 THEN Q := (OTHERS=0); ELSIF CLKEVENT AND CLK = 1 THEN IF EN = 1 THEN IF Q9 THEN Q := Q + 1; ELSE Q := (OTHERS=0); END IF; ELSE Q := Q ; END IF; END IF; IF Q = 1001 THEN COUT = 0; ELSE COUT = 1; END IF; DOUT= Q ; END PROCESS; END behav; 十进制计数控制模块仿真 十进制计数控制模块仿真结果