(数字电子技术）CH38组合电路的VHDL语言描述及仿真.pdf

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY decoder38 IS 3. 8 组合逻辑电路的VHDL 描述及其仿真 PORT(a : IN STD_LOGIC_VECTOR(2 DOWNTO 0); [ 例3 .8 .1 ] 3线-8线译码器的VHDL描述及仿真 y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decoder38; ARCHITECTURE one OF decoder38 IS BEGIN PROCESS (a) BEGIN CASE a IS WHEN 000 = y= WHEN 001 = y= WHEN 010 = y= WHEN 011 = y= WHEN 100 = y= WHEN 101 = y=