5 kgf（50 n）×1000次acetite as-3903 csp underfill.pptVIP

How about this business in future? The cost of CSP is going down like Wafer Level CSP. And Stacked CSP reduces mounting area and weight as the same with Flip Chip. In addition, Stacked CSP integrated IC chips can be System in Package itself and developed in short term, resulting in cost reduction. (Show a structure of Stacked CSP) Configuration example of triple- chip are; CPU(ASIC) + Flash memory(32M) + SRAM(4M) Flash memory(32M) +Flash memory(16M) +SRAM(4M) (Show comparison graph of area and weight) As you can see, mounting area and weight of Stacked CSP are smaller and lighter than Bare Ch