锁相技术译文翻.docVIP

锁相技术译文翻译 英文原文： An?On-Chip?All-Digital?Measurement?Circuit?to?Characterize?? Phase-Locked?Loop?Response?in?45-nm?SOI 译文： 45纳米SOI全数字片上测量电路表征锁相环响应特性 年级专业： 姓名： 学号： 2013 年 6 月 2 日 英文 中文 An?On-Chip?All-Digital?Measurement?Circuit?to?Characterize?Phase-Locked?Loop?Response?in?45-nm?SOI? Abstract—An?all-digital?measurement Circuit ,?built?in?45-nm?SOI-CMOS?enables?on-chip?characterization?of?phase-locked?loop?(PLL)?response?to?a?self-induced?phase?step. This?technique?allows?estimation of?PLL?closed-loop?bandwidth?and?jitter?peaking.??The?circuit?can be?used?to?plot?step-response?vs.ti