飞思卡尔半导体招聘IC研发实习生.PDF

飞思卡尔半导体招聘IC 研发实习生 飞思卡尔半导体总部位于美国德克萨斯州奥斯汀市，其设计、研发、生产及销售机 构遍布20 多个国家和地区。在创新、质量和注重实效的企业文化引领下，全球 18,000 名员工齐心协作、锐意进取。秉承让世界更智能的理念，我们始终是嵌入式 处理解决方案的领导者。 飞思卡尔在嵌入式处理解决方案领域处于全球领先地位，推动汽车电子、消费类 电子、工业电子以及网络设备市场向前发展。从微处理器和微控制器，到传感器、 模拟IC 以及连接器件——我们的技术和产品始终为创新奠定基础，让世界变得更 环保、更安全、更健康，让人们的联系更加紧密。 本次实习期为6-12 个月，针对2017 年及以后毕业的硕士研究生，实习生毕业后很 有可能成为飞思卡尔的正式成员，还等什么？赶紧报名！ 报名方式：大家可以将自己的简历以“工作地点-职位名称-就读学校-毕业年份”为标 题将简历发送至：campus@ ~ 具体职位信息如下： 1. Silicon Validation Intern Location: Shanghai Suzhou Responsibilities: - Apply skills and knowledge in both hardware and software to perform Pre or Post Silicon validation tasks for Freescale microcontroller products - To define the validation plan, and create or execute validation test - Design and layout the validation board to bring up new system for fresh IC - Work with other cross functional teams in China and oversea to specify, verify and improve SoC quality and timeliness to production Requirements: - Master or Bachelor Degree, electronic or microelectronic - Working knowledge in C/C++, Makefile - Big plus with experience in ARM M0, M0+ and M4 based MCU - Big plus with experience in IAR and CodeWarrior debugger Tool - With the FPGA development experience is plus - Fluent in writing and speaking English - Can work efficiently either in a team or an independent environment 2. IC Backend design intern Location: Shanghai Responsibilities: - Backend team of SDC MPG participates in chip level (from RTL-synthesis to GDS-TO) and block level backend design for SOC designs. - Responsible for low power embedded MCU soc design. - Major on chip and block level CPF definition, Logic/physical synthesis, Clock tree synthesis, place and routing, STA timing closure. - Responsible for Die size estimation, floor-planning, power planning and power analysis. - Responsible for