quartus ii 中常见warning 及解决方法(转载)（Quartus II中常见警告及解决方法（转载））.docVIP

quartus ii 中常见warning 及解决方法(转载)（Quartus II中常见警告及解决方法（转载）） Support original! I reprinted, you can download free 1.Found clock-sensitive, change, during, active, clock, edge, at, time, time, on, register, name Reason: vector, source, file, clock sensitive signals (such as data, allowing, clearing, synchronization, loading, etc.) change simultaneously on the edge of the clock. A clock sensitive signal cannot change at the edge of the clock. The consequence is that the result is incorrect. Measures: edit vector source file 2.Verilog, HDL, assignment, warning, at, location: truncated, value, with, size, number, to, match,, size, of, target (number Reason: in HDL design, the number of targets is set, such as: reg[4:0] a, and default to 32 bits, the number of digits to the right size Measure: if the result is correct, it needs no correction. If you dont want to see this warning, you can change the number of settings 3.All, reachable, assignments, to, data_out (10), assign,0, register, removed, by, optimization Reason: after the optimizer has been optimized, the output port is no longer functional 4.Following 9, pins, have, nothing, GND, or, VCC, driving, datain, port - changes, to, this,, connectivity, may, change, results, fitting Reason: ninth feet, empty or grounded or connected to the power supply Measures: sometimes the output port is defined, but the output is directly assigned to 0, which will be grounded and assigned 1 to the power supply. If these ports are used in your design, you can ignore these warning 5.Found, pins, functioning, as, undefined, clocks, and/or, memory, enables Reason: you have no constraint information as the PIN of the clock. You can set the settings for the corresponding PIN. Mainly refers to some of your pin in the circuit played a role in the clock tube, such as the flip-flop CLK pin, and this pin has no clock constraint, so QuartusII CLK as undefined clock. Measures: if CLK is not a clock, can add not clock constraint; if it is, can be add