An efficient algorithm for exploiting multiple arithmetic units：（一个高效的算法利用多个算术单元）.pdfVIP

R. M. Tomasulo An Efficient Algorithm for Exploiting Multiple Arithmetic Units Abstract: This paper describes the methods employed in the floating-point area of the System/360 Model 91 to exploit the existence of multiple execution units. Basic to these techniques is a simple common data busing and register tagging scheme which permits simultaneous execution of independent instructions while preserving the essential precedences inherent in the instruction stream. The common data bus improves performance by efficiently utilizing the execution units without requiring specially optimized code. Instead, the hardware, by looking ahead about eight instructions, automatically optimizes the program execution on a local basis. The application of these techniques is not limited to floating-point arithmetic or System/360 architecture. It may be used in almost any computer having multiple execution units and one or more accumulators. Both of the execution units, as well as the associated storage buffers, multiple accumulators and input/output buses, are extensively checked. Introduction After storage access time has been satisfactorily reduced execution of floating-point instructions in the IBM Sys- through the use of buffering and overlap techniques, even tem/360 Model 91. Obviously, one begins with multiple after the instruction unit has been pipelined to operate execution units, in this case an adder and a multi- at a rate approaching one instruction per cycle,1 there plier/divider. remains the need to optimize the actual performance of It might appear that achieving the concurrent operation arithmetic operations, es