5 A structured VHDL design method - Gaisler（5一个结构化的硬件描述语言(VHDL)设计方法Gaisler公司）.pdf

Fault-tolerant Microprocessors for Space Applications Jiri Gaisler 5 A structured VHDL design method 5.1 Introduction The VHDL language [22] was developed to allow modelling of digital hardware. It can be seen as a super-set of Ada, with a built-in message passing mechanism called sig- nals. The language was defined in the mid-1980’s as a respons to the difficulties of developing, validating and co-simulating increasingly complex digital devices devel- oped within the VHSIC[23] program. The main focus was to be able to write executable specifications, and allow specifications (or models) from different providers (compa- nies) to be simulated together. When the language was first put to use, it was used for high-level behavioural simula- tion only. ’Synthesis’ into VLSI devices was made by manually converting the models into schematics using gates and building blocks from a target library. However, manual conversion tended to be error-prone, and was likely to invalidate the effort of system simulation. To address this problem, VHDL synthesis tools that could convert VHDL code directly to a technology netlist started to emerge on the market in the begining of 1990’s. Since the VHDL code could now be directly synthesised, the development of the models was primarily made by digital hardware designers rather than software engi- neers. The hardware engineers were used to schematic entry as design method, and their usage of VHDL resembled the dataflow design style of schematics. The functionality was coded using a mix of concurrent statments and short processes, each decribing a limited piece of functionality such as a register, multiplexer, adder or state machine. In the early 1990’s, such a design style was acceptable since the complexity of the circu