A Structured VHDL Design Method - Gaisler（一个结构化的硬件描述语言(VHDL)设计方法Gaisler公司）.pdf

A Structured VHDL Design Method Jiri Gaisler CTH / Gaisler Research Outline of lecture Traditional ad-hoc VHDL design style Proposed structured design method Various ways of increasing abstraction level in synthesisable code A few design examples Traditional design methods Many concurrent statments Many signal Few and small process statements No unified signal naming convention Coding is done at low RTL level: Assignments with logical expressions Only simple array data structures are used Problems Slow execution due to many signals and processes Dataflow coding difficult to understand Algorithm difficult to understand No distinction between sequential and comb. signals Difficult to identify related signals Large port declarations in entity headers Modelling requirements We want our models to be: Easy to understand and maintain Simulate as fast as possible Synthesisable No simulation/synthesis discrepancies Abstraction of digital logic A synchronous design can be abstracted into two separate parts; a combinational and a sequential q Comb d q = f(d,q ) r DFF q r Clk Implementing the abstracted view in VHDL: The two-process scheme A VHDL entity is made to contain only two processes: one sequential and one combinational Two local signals are declared: register-in (r i n ) and register-out (r ) The full algorithm (q = f(d,r ))is performed in the combinational process The combinational process