小晶粒高效多晶硅片的电阻率测试偏差的分析研究.docVIP

小晶粒高效多晶硅片的电阻率测试偏差的分析研究 文章作者：刘海，张涛，胡动力，万跃鹏?等。 Hai Liu,Tao Zhang, Linyan Liu， Sheng Cao，Liang He，Dongli Hu，Yuepeng Wan LDK solar Co., Ltd, Economic Development Zone,Xinyu, Jiangxi, 338032, P.R.C * E-Mail: liuhai@ 摘要：本文分析了应用四探针法与涡流感应法测试硅多晶硅电阻率时，晶界对测试结果的影响。 ?? 实验表明，应用四探针法测试晶界处电阻率时，测试结果对探针的相对位置极为敏感；而应用涡流法的电阻率测试结果在晶界处偏高，测试偏差受涡流频率的影响。此外，对硅片的退火处理可以显著降低晶界处电阻率的测试偏差；而酸制绒工序会增加晶界处电阻率测试偏差。通过引入晶界电容阻抗的电路模型，得出了晶界电阻、晶粒尺寸、涡流频率等因素与电阻率测试偏差的对应关系。 ?? 实验与理论分析表明，高频率涡流感应法测试硅多晶晶界处的电阻率偏差较小，与体电阻率相符。 Abstract: The influence of the grain boundaries on resistivity measurements in multi-crystal silicon(mc-si) wafer was analyzed with four-probes and eddy current induction method,respectively. The experiments show that the resistivity result is extremely sensitive at the relative position of the probe and the grain boundary with four-probe method, and while with the eddy current induction method, the resistivity result at the grain boundaries is higher than at the other area,and is dependent on eddy current frequency . Besides, annealing treatment can significantly reduce the deviation of resistivity testing results at the grain boundary, and in contrast, acid texturing process will increase it. In this paper, a model based on grain boundary capacitance impedance circuit ?was proposed, and a hypothetical relationship of the deviation of resistivity results with grain boundary resistance, grain size and eddy current frequency factor were obtained. Experiments and theoretical analysis show that with higher frequency eddy current induction method, the deviation of resistivity due to grain boundary is smaller and the results are closer to the bulk resistance.? 关键词：晶界 电阻率 涡流感应频率 晶界势垒 0前言 单晶硅片由于其均匀的电化学性能，利用四探针或涡流感应法可测量得到稳定和精确的电阻率值。而由于晶界势垒和界面态这两方面的影响，多晶硅片的电化学性能在晶界处发生突变，当跨越晶界或邻近晶界测试电阻率时，测试结果会存在不同程度的偏差。报道表明[1]，因晶界势垒的存在，四探针测试电阻率时会受晶界与探针位置的影响；涡流法感应测试电阻率时会受到晶界形态的影响。 ??? 为了减少晶界对电阻率测试的影响，目前行业内在测试电阻率时，会尽量选择在硅片表面大晶粒内测量，但仍旧有几点无法避免： 1、硅多晶定向凝固生长时熔体对流较差，电阻率在生长界面的分布并不完全均匀； 2、晶体内部的晶界以及表面的小角度晶界用肉眼无法观测到，同样会影响到电阻率测试； 3、该方法不