关于微处理器.ppt

Parallel Computer Architecture并行计算机体系结构Lecture 13 May 18, 2009 Wu junmin (jmwu@ustc.edu.cn) Overview Review of Lec11 SMP中的同步 MPP 当前高性能计算机介绍 高性能计算机未来 Preliminary Design Issues Design of cache controller and tags Both processor and bus need to look up How and when to present snoop results on bus Dealing with write-backs Overall set of actions for memory operation not atomic Can introduce race conditions Atomic operations New issues deadlock, livelock, starvation, serialization, etc. Contention for Cache Tags Cache controller must monitor bus and processor Can view as two controllers: bus-s