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Challenges and Realities of Advanced Node (高级节点的挑战和现实)
Challenges and Realities of Advanced Node
Manufacturing
Srinivasa R Banna PhD
Fellow Director of Advanced Device Architecture
13 July 2016
Outline
• Motivation
• Pitch Scaling
– Fin, Gate, MOL Metal
• Material Innovation
–Contacts
–Air gaps
–New channel materials
• New Device Architectures
–GAA
–Steep Subthreshold
• Summary
GLOBALFOUNDRIES 2
Motivation (1/2)
SoC Performance/Power Trade-off
1.40
)
u
.
1.30
a
( New
) e
u
. c Node
a 1.20
( n
y a
c
n ~
e m 20%
1.10
u r
q o
r
F f
r ~ Current
e 35%
g e
1.00
a P Node
r
e
v C
A
0.90
o
S
0.80
0.60 0.80 1.00 1.20 1.40 Srini Banna CiCC 2015
SoC Power (a.u)
Total Power (a.u)
• ≥ 20% performance uplift at iso power
• ≥ 35% power reduction at iso performance
• Enable lowest Vmin highest Vmax
GLOBALFOUNDRIES 3
Motivation (2/2)
Design Technology Co-Optimization
Multiples of CPP
• Cell height
– Metal pitch
– Fin Pitch T
E
F
) p
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