Topic_04_behavioral_Synthesis_08课件.pptVIP

Behavioral Modeling Synthesis Views;Semantics: Sequential Concurrent Statements;Signal Assignments;VHDL Design Styles;Processes in VHDL;Anatomy of a Process;The Process Sensitivity List;PROCESS with a SENSITIVITY LIST;Process statements/Wait statement;Process/Wait Statements;testing: PROCESS BEGIN test_vector=“00”; WAIT FOR 10 ns; test_vector=“01”; WAIT FOR 10 ns; test_vector=“10”; WAIT FOR 10 ns; test_vector=“11”; WAIT FOR 10 ns; END PROCESS; ;Synthesis Point of View ;Sequential Statements:If Statement;If statement and Latches;Sequential statements: An Example;If statement (cont);If Statements (cont);Example: Priority Encoder;If Statements in Series: Assigning to Same Object;If..Elsif: Assigning To Same Object;An other Equivalent formulation for If Statement;IF Else ;Warning: Signal Assignment in Processes;Signal Assignment in Processes: Incorrect Solution;A correct solution;Case Statement;Case Statement;CASE STATATENET (con);Example ;IF vs CASE statement;Latch Synthesis of Case Statements;Case Statement Latch Example;Case Statement Latch Avoidance Example;Sequential Statementsloop Statement;Forms of iteration schemesloop statements;Rules for Loop syntax;Example;PARITY: Block Diagram;Other sequential Statements;Other sequential statements:NEXT statement;For..Loop Statement Latch Example;For..Loop Statement Latch Example Clarification;For..Loop Latch Avoidance Example;Primary level of abstraction in VHDL is the entity In a behavioural description, the entity is defined by its responses to signals or input similar to a black box;Example: ;Clocked ProcessesSequential Circuit Modelling;Clock reference in a Process;Clock Description in VHDL 2;Clocked Processes;Synthesis of Previous VHDL;Example 2;Example;The VHDL code below demonstrates the link between the hardware and the location of the statement assignment in the process.; What happens if the B 2 statement is moved to be within the clock scope?;Synthesis of Variables;Flip Flo