EDA用VHDL语言设计一个2-4译码器.docVIP

2-4译码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder 2 _4 IS PORT( a:IN STD_LOGIC_VECTOR(1 DOWNTO 0); s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END decoder2_4; ARCHITECTURE Behavioral OF decoder2 _4_t IS BEGIN PROCESS(sel) BEGIN CASE a IS WHEN 00=s=”0001”; WHEN 01=s=”0010”; WHEN 10=s=”0100”; WHEN 11=s=”1000 “; WHEN OTHERS=s=’’0000” END CASE; END PROCESS; END Brhavioral; 4选1数据选择器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sel4 IS PROT(d:IN STD_LOGIC_VECTOR(3DOWNTO 0); a:IN STD_LOGIC_VECTOR(1 DOWNTO 0); s:OUT STD_LOGIC); END sel4: ARCHITECTURE Behavioral OF sel4 IS BEGIN ROCESS(a,d) BEGIN CASE a IS WHEN 00=s=d(0) WHEN 01=s=d(1) WHEN 10=s=d(2) WHEN 11=s=d(3) “; WHEN OTHERS=s=’Z’ END CASE; END PROCESS; END Brhavioral; 100进制加法计数器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter IS PORT(clk,en,load,rst:IN STD_LOGIC d;IN STD_LOGIC_VECTOR(6 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(6DOWNTO 0): END counter 100; ARCHTECTURE Behavioral OF counter 100 IS signal qtemp:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN PROCESS(clk,d,en,load,rst) BEGIN IF rst= ’1’ THEN qtemp=; ELSIF rising-edge(clk) THEN\ IF en=’1’ THEN IF load=’1’ THEN qtemp=d, ELSIF qtemp=”1100011” THEN qtemp=; ELSIF qtemp=qtemp+’1; END IF; END IF; END IF; END PROCESS; q=qtemp; END Behavioral; 8位从高至低串入串出移位寄存器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY shift.register IS PORT( d,clk:IN STD_LOGIC; q:OUT STD_LOGIC); END d shift.register; ARCHITECTURE Behavioral OF shift.register IS signal qtemp:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(d,clk) BEGIN IF rising-edge(clk) THEN q=dtemp(0); dtemp=ddtemp(7 DOWNTO 1);