数_模混合信号设计验证中主要问题的分析_邓军勇.pdfVIP

Techn l gy C lumn / 邓军勇, 曾泽沧, 蒋林 ( 西安邮电学院计算机系, 西安710061) : 数/ 模混合片上系统的发展日新月异, 为保证产品良率, 芯片投片前的验证是片上系 统设计流程 的关键环节在数/ 模混合信号验证方法 , 如何对整 个混合信号设计的数字模块 和模拟模块进行划分, 以及如何完成两类模块间数字信号和模拟信号的相互映射传输, 是混合验 证 的两 个主要问题以 一个1 2 解复用的混合信号设计为例, 对这两 个问题进行了分析讨论, 同时从工具角度对两类仿真器之间的同步做了论述, 最后采用Cadence 的Virtu s AMS Simulat r 工具进行了完整的混合信号验证 : 数/ 模混合信号; 协同验证; 设计划分; 信号映射; 同步 : TN47 ! ! : A ! ! : 1003353X ( 2007) Analysis on Primary Issues in Digital/ Analog MixedSignal Verification DENG Juny ng, ZENG Zecang, JIANG Lin ( Computer Department, Xi∀ anInstitute of Posts Telecommunications, Xi∀ an 710061, China) Abstract: With the rapid devel pment f digital/ anal g mixedsignal system nachip ( SOC) , the verificati n bef re tape ut is a critical phase during the design fl w in rder t guarantee the pr ducts yield. Tw primary issues in the verificati n are: h w t partiti n the digital m dules and anal g m dules, and h w t map and transfer the signals between the tw different m dules. The analysis n the tw issues with a mixedsignal design was presented: the 1 2 demultiplexer, the wh le verificati n was c mpletesd with the cadence virtu s AMS simulat r. The synchr nizati n between the tw different simulat rs at the p int f t ls∀ devel pment view was analyzed. The c mplete mixed signal was validated by Virtu s AMS Simulat r f Cadence. Key words: digital/ anal g mixedsignal; c verificati n; design partiti n; signal mapping; synchr nizati n [ 1] SOC 1! 引言 / ,