第0讲 逻辑电路ABC.ppt

LOGICAL CIRCUITS A B C 逻 辑 电 路 基 础 Basic Logic Elements Logic Level TTL : VCC=5V±5% 0=0-0.7V 1=2.4 ~ 5V CMOS: VDD=3 ~ 8V (Lower to1.8 or 0.9V) 0=0~0.3VDD, 1=0.7~1VDD TTL and CMOS Transistors Basic Logic Elements Simple Gates Inverter B = A ( B = !A) NAND !C = A * B Basic Logic Elements NOR !C = A # B Three Status Gate D Flip-Flop If CLK = High, Output = Input, i.e. Q=D When LE from High to Low and keeps low, Q keeps previous Status It is called Data are LATCHed by the Falling edge of CLK CLK Q Q=D Q Keeps not change Time Basic Logic Elements 2 to 4 Decoder: RS Flip-Flop and other Logical Integrated Circuits 一个概念CPU 示意性CPU指令表 外部事件叫中断和CPU清中断 Instruction Set 数的表示法 8位无符号数， 可以表示0～255的256正整数 例如：二进制数： =128+64+8＝200 8位有符号数，将最高位看成是符号位，0表示正数，1表示负数，表达范围－128～＋127 负数用补码表示，－1＝0－1＝0xFF=$FF 补码＝反码＋1； 0x01=$01的反码=$FE, 故$FE+1=$FF=-1 看成是无符号数就是200，而看成是有符号数就是一个负数： -56。 以上约定可扩展到16位、24位、32位 数的运算 Memory Map 68HC11/12 CPU * 2 - e b c N type Vdd Vss g g N type P type On g = High On b = High On g = Low Off b = Low A B B A A B C A B C A B C In Out C C C In Out A B D CLK Q Q CLK D Q Q From Logical to Sequential Circuits D CLK Q Q Set Reset S0 S1 S2 S3 A B L H H H H L H H H H L H H H H L 0 0 0 1 1 0 1 1 S0 S1 S2 S3 A B 加减 左移 右移 与或 多路开关 C B A S0 S1 S2 S3 Transfer F = A F = A+1 Add F = A + B F = A + B + 1 Sub F = A – B – 1 F = A – B Dec F = A – 1 And F = A ^ B Or F = A | B Not F = -A Compliment F = !A F = Logical shift right A F = Rotate shift right A F = Rotate shift right A with Carry F = Arithmetic shift right A F = Logical shift left A F = Rotate shift left A F = Rotate shift left A with Carry F = Arithmet