a fast algorithm for transistor folding晶体管折叠的快速算法.pdfVIP

VLSI DESIGN (C) 2001 OPA (Overseas Publishers Association)N.V. 2001, Vol. 12, No. 1, pp. 53-60 Published by license under Reprints available directly from the publisher the Gordon and Breach Science Photocopying permitted by license only Publishers imprint. Printed in Malaysia. A Fast Algorithm for Transistor Folding* EDWARD Y. C. CHENG and SARTAJ SAHNI* Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL 32611-6120 (Received 13 July 1999; In final form 20 September 1999) Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m2 log m) algorithm to optimally fold rn transistor pairs. In this paper we develop an O(rn2) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000). Keywords and Phrases: Transistor folding; Row-based design; Area minimization; Complexity 1. INTRODUCTION O(m6), where m is the number of transistor pairs, dynamic programming algorithm for the general In high-performance circuit design, the transistor transistor folding problem. (If onl