基于fpga流水线分布式算法的fir滤波器的实现 - 世（Implementation of FIR filter based on pipelined distributed algorithm in FPGA）.docVIP

基于fpga流水线分布式算法的fir滤波器的实现 - 世（Implementation of FIR filter based on pipelined distributed algorithm in FPGA） I carefully organize the documents, documents from the network I just sort of If there is an error Please check your! The realization of FIR filter line distributed algorithm based on FPGA Abstract: This paper proposes a novel encoding gate array (FPGA) based on design and implementation of linear FIR digital filter based on window function method According to a sixteen order low pass FIR digital filter circuit as an example to illustrate the design process of the Virtex-E series chip of Xilinx company The key to achieve FIR filter in FPGA multiply This will multiply into a distributed lookup table algorithm The design of the circuit through the software test and hardware simulation The results show that the circuit is correct and reliable Can meet the design requirements Keywords: FIR window FPGA filter algorithm of distributed pipeline With the widespread application of the digital technology Based on field programmable gate array (FPGA) ASIC devices represented by the rapid popularization and development Device integration and speed in high speed long FPGA not only has the high logic gate array density and high reliability Also has the encoding logic device user programmable features It can reduce the design and maintenance of the risk diminish cost of output To shorten the design cycle The distributed algorithm is to achieve the multiply add operation method for the purpose of It is different with the traditional algorithm of multiply is part of the implementation of the order of different product operation Simply Distributed algorithm in multiply function is completed by the input data of each corresponding position of partial product pre advanced formation of the corresponding partial product sum And then accumulate to form the final results in the departments of product But the traditional algorithm is wait until all together to complete the product and