TI的锁相环的datasheet：pll1705.pdfVIP

SLES046A − AUGUST 2002 − REVISED SEPTEMBER 2002 FEATURES APPLICATIONS DVD Players 27-MHz Master Clock Input DVD Add-On Cards for Multimedia PCs Generated Audio System Clock: Digital HDTV Systems − SCKO0: 768 f (f = 44.1 kHz) S S Set-Top Boxes − SCKO1: 384 f , 768 f (f = 44.1 kHz) S S S − SCKO2: 256 f (f = 32, 44.1, 48, 64, 88.2, S S DESCRIPTION 96 kHz) † † − SCKO3: 384 f (f = 32, 44.1, 48, 64, 88.2, The PLL1705 and PLL1706 are low cost, phase-locked S S 96 kHz) loop (PLL) multiclock generators. The PLL1705 and PLL1706 can generate four system clocks from a 27-MHz Zero PPM Error Output Clocks reference input frequency. The clock outputs of the Low Clock Jitter: 50 ps (Typical) PLL1705 can be controlled by sampling frequency-control pins and those of the PLL1706 can be controlled through Multiple Sampling Frequencies: