StratixV器件中的精度可调DSP模块.pdf

Stratix V器件中的精度可调DSP模块 3 2013.05.06 SV51004 订阅 反馈 本章描述了Stratix® V器件中的精度可调数字信号处理(DSP)如何被优化以支持高性能DSP应用中的 更高比特精度。 相关链接 Stratix V Device Handbook: Known Issues 列出了对Stratix V器件手册章节规划的更新。 特性 每个Stratix V精度可调DSP模块占一个逻辑阵列模块(LAB)行高。 Stratix V精度可调DSP模块具有以下特性： • 高性能、功耗优化和完整寄存的乘法操作 • 9-bit，18-bit，27-bit和36-bit字长 • FFT的18 x 25复数乘法 • 浮点算术格式 • 内置加法，减法和64-bit累加单元用于综合乘法结果 • 级联18-bit 和27-bit 输入总线以形成滤波应用的抽头延迟线(tap-delay line) • 级联64-bit输出总线，在没有外部逻辑支持的情况下将输出结果从一个模块传播至下一个模块 • 用于实现对称滤波器18-bit 和27-bit模式的硬核预加器 • 用于滤波实现的内部系数寄存器块的18-bit和27-bit支持 • 具有分布式输出加法器的18-bit和27-bit脉动有限脉冲响应(FIR)滤波器 相关链接 Stratix V Device Overview 提供了关于每个Stratix V器件中乘法器数量的详细信息。 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes Registered no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 Innovation Drive, San Jose, CA 95134