VHDL智力抢答器设计.docVIP

抢答鉴别电路myqdjb的vhdl源程序 --myqdjb.vhd library ieee; use ieee.std_logic_1164.all; entity myqdjb is port(clr: in std_logic; a,b,c,d: in std_logic; a1,b1,c1,d1: out std_logic; states: out std_logic_vector(3 downto 0)); end entity myqdjb; architecture art of myqdjb is constant w1: std_logic_vector:=0001; constant w2: std_logic_vector:=0010; constant w3: std_logic_vector:=0100; constant w4: std_logic_vector:=1000; begin process(clr,a,b,c,d) is begin if clr=1then states=0000; elsif(a=1and b=0and c=0and d=0)then a1=1; b1=0;c1=0;d1=0;states=w1; elsif(a=0and b=1and c=0and d=0)then a1=0; b1=1;c1=0;d1=0;states=w2; elsif(a=0and b=0and c=1and d=0)then a1=1; b1=0;c1=1;d1=0;states=w3; elsif(a=0and b=0and c=0and d=1)then a1=0; b1=0;c1=0;d1=1;states=w4; end if; end process; end architecture art; 计分器电路yjfq的vhdl源程序 --yjfq.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yjfq is port(rst:in std_logic; add:in std_logic; chos:in std_logic_vector(3 downto 0); aa2,aa1,aa0,bb2,bb1,bb0:out std_logic_vector(3 downto 0); cc2,cc1,cc0,dd2,dd1,dd0:out std_logic_vector(3 downto 0)); end entity yjfq; architecture art of yjfq is begin process(rst,add,chos)is variable points_a2,points_a1:std_logic_vector(3 downto 0); variable points_b2,points_b1:std_logic_vector(3 downto 0); variable points_c2,points_c1:std_logic_vector(3 downto 0); variable points_d2,points_d1:std_logic_vector(3 downto 0); begin if(addevent and add=1) then if rst=1then points_a2:=0001;points_a1:=0000; points_b2:=0001;points_b1:=0000; points_c2:=0001;points_c1:=0000; points_d2:=0001;points_d1:=0000; elsif chos=0001then if points_a1=1001then points_a1:=0000; if points_a2=1001then points_a2:=0000; else points_a2:=po