EDA第3章补充2-毛刺.ppt

建立时间和保持时间 Example 1 My Waveform Input Correct Waveform Example 2 How to fix the problem Conclusion If the Setup/Hold time error happen on the Input Register (Example 1) run the Setup/Hold time Matrix to get information adjust the Input Waveform but double confirm with the real time operation signal If the Setup/Hold time error happen between Two Register (Example 2) run the Register Performance to get Fmax make sure that the input clock frequency is less than or equal to the Fmax 2. Design of Combinational Circuit What is Combinational Circuit Combinational Circuit if Outputs at a specificed time are a function only of the INPUTS at that time example of combinational circuit address decoders multiplexers adders The Simplest Combinational Circuit Nothing can be simplest than 2 input AND Gate or 2 input OR Gate 2 input AND/OR gate is as simple as 1+1 = 2 2 input AND Gate Take a closer look 续 Key Point of Combinational Design Design with 2 input AND gate is not as easy as 1+1=2 We need to consider the Trace Delay and Gate Delay for Combinational Logic Functional : The output of C is “0” Timing : The output of C has a Glitch with 3ns width In this example, the 3ns Glitch is caused by Trace Delay Engineer Design Circuit work with Timing not Functional only 续 If you want your cirucit work RELIABLE, you need to consider TIMING FACTOR Go back to the First Example Now, we all know that a 2 input AND gate when involve with timing is not as easy as 1+1=2 Reminder When Glitch will happen when more than one signals change at the same time When you design combinational logic Glitch happen is expected If you do not get one, you are lucky only A good engineer always remember that Combinational logic will have GLITCH Glitch issue If we know how Glitch generate we can calculate the exact time when the Glitch comes out we can calculate the exact pulse width of the Glitch Special care must be pay attention when the Combinational Logic output is used for CLEAR of the Flip-Flop